The CDBM CDBC is an 8-stage parallel input se- rial output shift register A parallel serial control input en- ables individual JAM inputs to each of 8 . Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise . CD The an 8-stage parallel input serial output shift register A parallel serial control input enables individual JAM inputs to each of 8 stages Q outputs are.
|Published (Last):||26 July 2005|
|PDF File Size:||14.75 Mb|
|ePub File Size:||1.68 Mb|
|Price:||Free* [*Free Regsitration Required]|
HTTP This page has been moved
CD BE – Understanding the truth table. I’ve found some code online but unfortunately it is not helpful for understanding how the shift register works.
Basically I’m duplicating what a MCU does but at very slow speed. I did this before with a 74HC shift register and it clarified for me how it functions, but with the CD it’s a different story. Data Sheet for the CD Here’s how I use the switches to duplicate what the MCU does: Input s n – HIGH I did this with one of the 8 inputs and in another test with two inputs simultaneously 3. Input s n – LOW 5. PE – LOW 6.
While doing the tests I wrote down the output state of Q8. I’m not sure if this is the correct way to do it but I got some results that I don’t understand. According to the output table image CD – Datasheett output. What does Q1 Internal mean? What does Qn-1 do?
I’ve just updated the schematic image. The first one was wrong, the 8 input switches should be connected to VDD, not ground. CD – truth table. CD – Q8 output.
CD (BE) – Understanding the truth table
CDBE with buttons and leds. MarkT Brattain Member Posts: All bets are off until you debounce the push button driving the clock input – you will be getting anything from 1 to hundreds of edges everytime you press it at the moment.
Mechanical switches dayasheet never drive logic clocks directly for this reason! MarkT on Oct 06, JoeN Edison Member Posts: I read the truth table simply. Here is it in English. Under these conditions, the chip does not advance these 8 bits at all and SER IN is completely ignored. This is called a “preset” function. Q7 goes into Q8.
In either case, after the clock rises, Q6, Q7, and Q8 are available on their respective output pins. Clock falling doesn’t do datasyeet thing, as you would expect.
Is this not happening? Have you hit all pins with a logic probe to make sure they have the voltage you think they do? That is what the data sheet says, at least.
It looks like catasheet weird serial-in, last-three-bits-out, with parallel 8 bit preset shift register to me.
I will never ask you to do anything that I wouldn’t do myself. CDBE with buttons and leds Q8. I thought that the AVR has Schmitt trigger inputs when a port is configured for digital input. JoeN on Oct 09,